The manufacture of semiconductor chips requires the use of masks that are derived from the physical design of the chips. Physical design, however, is a very laborious and time consuming process. The process typically involves synthesizing control logic circuits into a gate level design, retrieval of the gate's characteristics from a design library for the technology, and arrangement of the gates in a desired configuration using appropriate placement and routing tools. One method for placing the components of a memory circuit is the technique of manually drawing polygons that represent these components. One problem with this technique, however, is the unavailability of any means for continuous tuning of the circuit in response to changes in the dimensions of the circuit (e.g., changes of width, length, ground and power busses, etc.). If the logic or design changes in the midst of the design cycle, it is difficult to change the already finished layout. Clearly, present techniques provide insufficient performance and automation for today's needs.
The polygon approach, also known as "polygon pushing", presents throughput problems, is extremely error prone, requires iterative verification, is technology-dependent, can not be compacted and is difficult to reuse. Also, graphical hand drawn polygon representations are difficult to parameterize unless the polygon shape manipulation is software controlled. Further, the ability to adjust layout at the gate level is not available.
It can be seen, therefore, that alternative methods are needed to improve the circuit designer's productivity.